The present invention relates to integrated circuit design methods and, in particular, to a method for identifying errors and characterizing integrated circuit designs at an architectural level.
The complexity of modern integrated circuits has led to the development of architecture-based designs which use high level design methods to decrease design cycle time. For example, a typical high-level design method uses an algorithmic description of the behavior of an integrated circuit to generate a register transfer level (RTL) hardware implementation of the circuit. The RTL implementation is produced by executing a plurality of design tasks such as scheduling, resource allocation, binding (mapping behavioral statements to specific hardware components), and control unit generation.
The design tasks work interdependently to produce a design database that represents the integrated circuit at multiple architectural levels. In such a design method, design errors can be introduced during the design both by the designer and by the automated design tasks. The more complex the design the more difficult it is to correlate behavioral statements with RTL components in order to modify the design database to correct design errors. For example, if a scheduling error is introduced into the design, either a behavioral statement, an RTL component or system timing may need modification. Identifying the appropriate statement, component or timing signal to modify is often a time consuming, trial-and-error process.
To characterize the system's dynamic functionality, the system is simulated to verify that the operation is consistent with constraints which are not modeled with behavioral statements, such as propagation delay or component counts. Simulation is performed on the RTL implementation and produces data at the RTL or hardware architectural level.
Prior art error identification methods use a set of predefined error-checking rules to test design data only after the design is complete. Such methods are inefficient because the entire database is tested each time the method is executed. Because of the interdependency of the design tasks, if an error is introduced at an early stage in the design, the error often propagates into the data produced by subsequent design tasks. Multiple errors that must be identified and corrected are thereby generated from the original error. The result is an inefficient use of design and computing resources.
When the RTL implementation is simulated, data is produced that represents the system at a hardware level, whereas designers often are most familiar with the behavioral description of the system. As a result, design efficiency is further reduced to allow the designer to become more familiar with the RTL implementation.
Hence, there is a need for a more efficient method of analyzing the static and dynamic operation of a system that allows a designer to analyze the system at the earliest stages of a design and at the most appropriate architectural levels.